Intel HD500 Overclock Apollo Lake Soc with N3450. Is it possible? change ratio
Hi, i have many dubts about the possibility to change frequency at intel HD500: i have started reading intel datasheet for Apollo Lake and under chapter P-unit, I've noticed that is possible to read\write the ratio power of GPU (RW), page 1864 volume2.
I also noticed that with old video driver (before Feb 2018) GPU can go up to 700MHz only when cpu load is lower than full stress; while with the newer gpu driver the gpu goes up to 450MHz with aida stress test so the newer driver manages in a different way the GPU ratio directly from windows.
GT Hardware P-state control request is located MEM register 32bit offset 8068h (P_CR_GT_HWP_REQ_0_2_0_GTTMMADR)
and 7-0bit are RW and include Quality of service P-state: the gt driver programs this to definite a desidered performance floor. This floor is useful as a hint to power and thermal control algorithms to balance system resources appropriately in order to ensure a minimum graphics performance floor. Described in 16.67MHz reference clock units,e.g. a ratio of 24 results in a clock frequency of 400MHz.
Does any know how to access to this memory part? I'm using Rweverything program but i can understand how to insert the correct address.
I belive should calculate address mixing my data,like reported in other intel document, where Memory address is given by PCI Express Configuration Register (ex. F0000000h)+ Bus Number (ex.15h)+ Device Number(ex.00h)+ Function Number (ex.05h)+ Register Offset (ex.84h)...total memory address F1505084h.
So if VGA is Bus 00, Device 02, Function 00 how can access to MEM register?
I also noticed that with old video driver (before Feb 2018) GPU can go up to 700MHz only when cpu load is lower than full stress; while with the newer gpu driver the gpu goes up to 450MHz with aida stress test so the newer driver manages in a different way the GPU ratio directly from windows.
GT Hardware P-state control request is located MEM register 32bit offset 8068h (P_CR_GT_HWP_REQ_0_2_0_GTTMMADR)
and 7-0bit are RW and include Quality of service P-state: the gt driver programs this to definite a desidered performance floor. This floor is useful as a hint to power and thermal control algorithms to balance system resources appropriately in order to ensure a minimum graphics performance floor. Described in 16.67MHz reference clock units,e.g. a ratio of 24 results in a clock frequency of 400MHz.
Does any know how to access to this memory part? I'm using Rweverything program but i can understand how to insert the correct address.
I belive should calculate address mixing my data,like reported in other intel document, where Memory address is given by PCI Express Configuration Register (ex. F0000000h)+ Bus Number (ex.15h)+ Device Number(ex.00h)+ Function Number (ex.05h)+ Register Offset (ex.84h)...total memory address F1505084h.
So if VGA is Bus 00, Device 02, Function 00 how can access to MEM register?
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