10 bit RockChip bull shit.
I don't want to agitate stinky water but I think that RockChip explanation is a bull crap. I didn't found any proof that RK3288 HDMI interface output 10bit per color when set to 4K resolution at 60 fps. On the contrary.
From file containing captured state of HDMI interface registers values supplied by kaefert we know that:
In every step neccessary to send input video through HDMI interface and to create output video there are settings indicating that color depth is set to 24 bits (8 bit per three primary color channels).
1. Color Space Convertion which is neccessary because input color space is RGB_0_255 and output video is YCbCr444 is enabled (reg. #4004h MC_FLOWCTRL value is 0x01) and coefficient table (reg #4102h-411bh) is set as CSC_RGB_0_255_TO_ITU709_16_235_8BIT and not CSC_RGB_0_255_TO_ITU709_16_235_10BIT as well pixel color depth is set to COLOR_DEPTH_24BIT.
2. HDMI Video Packetizer doesn't pack pixels which would be neccesary in 30 bit color mode (10 bpc) also 8BIT_BYPASS is enabled which is only available in 24 bit color mode (8 bpc)
I realy don't know what to make of that but "10 bit" is rather some smoke screen over other problems similar to this one: YUV420 color space in HDMI video output mode will probably newer be used because EDID doesn't have space for that setting and it is the source of HDMI output modes for RK3288 SoC.
If you can then provide me with similar data as kaefert from you setup with Panasonic UHD TV.
P.S. RK3288 HDMI 2.0 and 10 bit color depth?
Fragment of rk3288_hdmi_video_frameComposer function in rk3288_hdmi_hw.c from FireFly GIT.
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Originally posted by Rayzin
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From file containing captured state of HDMI interface registers values supplied by kaefert we know that:
Code:
Checking Identification Registers base address 0x0000Reg_off: 0x4 = CONFIG0_ID: 0xbf (191) => Available: HDMI1.4 = 1; CSC = 1; HDCP = 1; Reg_off: 0x5 = CONFIG1_ID: 0x22 (34) => HDMI2.0 = 1 Reg_off: 0x6 = CONFIG2_ID: 0xc2 (194) => HDMI PHY TYPE: MHL Checking Video Sampler Registers base address 0x0200 Reg_off: 0x0 = TX_INVID0: 0x01 (1) => Internal data enabled signal = 0; Video mapping = 1 => VIDEO_RGB444_8BIT Checking Video Packetizer Registers base address 0x0800 Reg_off: 0x1 = VP_PR_CD: 0x00 (0) => Color Depth = 0 => COLOR_DEPTH_24BIT_DEFAULT; Pixel Repet factor = 0 times Reg_off: 0x4 = VP_CONF: 0x46 (70) => Bypass enabled = 1; Pixel pack enabled = 0; Pixel repet enabled = 0; YCC422 enabled = 0; Bypass selected = 1; OUTPUT selected = OUT_FROM_8BIT_BYPASS Checking Frame Composer Registers base address 0x1000 Reg_off: 0x19 = FC_AVICONF0: 0x42 (66) => FC RGC YCC_2 (HDMI 2.0) = 0; FC active format = 1; FC RGC YCC mode = 2 => AVI_COLOR_MODE_YCBCR444 Reg_off: 0x1a = FC_AVICONF1: 0xa8 (168) => FC COLORIMETRY = 2 => AVI_COLORIMETRY_ITU709; FC picture aspec ratio = 2 => AVI_CODED_FRAME_ASPECT_16_9; FC active asperc ratio = 8 => ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME Reg_off: 0x1b = FC_AVICONF2: 0x10 (16) => FC extended Colorimetry = 1; FC quantization range = AVI_QUANTIZATION_RANGE_DEFAULT; FC NUN pic scale = 0 Checking Color Space Converter Registers base address 0x4100 Reg_off: 0x0 = CSC_CFG: 0x00 (0) => Color Space Converter interpolation mode = 0; Color Space Converter decimation mode = 0; Checking Identification Registers base address 0x0000 Reg_off: 0x4 = CONFIG0_ID: 0xbf (191) => Available: HDMI1.4 = 1; CSC = 1; HDCP = 1; Reg_off: 0x5 = CONFIG1_ID: 0x22 (34) => HDMI2.0 = 1 Reg_off: 0x6 = CONFIG2_ID: 0xc2 (194) => HDMI PHY TYPE: MHL Checking Video Sampler Registers base address 0x0200 Reg_off: 0x0 = TX_INVID0: 0x01 (1) => Internal data enabled signal = 0; Video mapping = 1 => VIDEO_RGB444_8BIT Checking Video Packetizer Registers base address 0x0800 Reg_off: 0x1 = VP_PR_CD: 0x00 (0) => Color Depth = 0 => COLOR_DEPTH_24BIT_DEFAULT; Pixel Repet factor = 0 times Reg_off: 0x4 = VP_CONF: 0x46 (70) => Bypass enabled = 1; Pixel pack enabled = 0; Pixel repet enabled = 0; YCC422 enabled = 0; Bypass selected = 1; OUTPUT selected = OUT_FROM_8BIT_BYPASS Checking Frame Composer Registers base address 0x1000 Reg_off: 0x19 = FC_AVICONF0: 0x42 (66) => FC RGC YCC_2 (HDMI 2.0) = 0; FC active format = 1; FC RGC YCC mode = 2 => AVI_COLOR_MODE_YCBCR444 Reg_off: 0x1a = FC_AVICONF1: 0xa8 (168) => FC COLORIMETRY = 2 => AVI_COLORIMETRY_ITU709; FC picture aspec ratio = 2 => AVI_CODED_FRAME_ASPECT_16_9; FC active asperc ratio = 8 => ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME Reg_off: 0x1b = FC_AVICONF2: 0x10 (16) => FC extended Colorimetry = 1; FC quantization range = AVI_QUANTIZATION_RANGE_DEFAULT; FC NUN pic scale = 0 Checking Color Space Converter Registers base address 0x4100 Reg_off: 0x0 = CSC_CFG: 0x00 (0) => Color Space Converter interpolation mode = 0; Color Space Converter decimation mode = 0; Reg_off: 0x1 = CSC_SCALE: 0x40 (64) => Color Space Converter color depth = 4 => COLOR_DEPTH_24BIT; Color Space Converter scale = 0
1. Color Space Convertion which is neccessary because input color space is RGB_0_255 and output video is YCbCr444 is enabled (reg. #4004h MC_FLOWCTRL value is 0x01) and coefficient table (reg #4102h-411bh) is set as CSC_RGB_0_255_TO_ITU709_16_235_8BIT and not CSC_RGB_0_255_TO_ITU709_16_235_10BIT as well pixel color depth is set to COLOR_DEPTH_24BIT.
2. HDMI Video Packetizer doesn't pack pixels which would be neccesary in 30 bit color mode (10 bpc) also 8BIT_BYPASS is enabled which is only available in 24 bit color mode (8 bpc)
I realy don't know what to make of that but "10 bit" is rather some smoke screen over other problems similar to this one: YUV420 color space in HDMI video output mode will probably newer be used because EDID doesn't have space for that setting and it is the source of HDMI output modes for RK3288 SoC.
If you can then provide me with similar data as kaefert from you setup with Panasonic UHD TV.
P.S. RK3288 HDMI 2.0 and 10 bit color depth?
Fragment of rk3288_hdmi_video_frameComposer function in rk3288_hdmi_hw.c from FireFly GIT.
Code:
[COLOR=#999988][FONT=Consolas][I]// If sink max tmdsclk is lower than 340MHz, we [/I][SIZE=2]are[/SIZE][I] limited to 1.4b spec.
[/I][/FONT][/COLOR][COLOR=#333333][FONT=Consolas][B]if[/B][/FONT][/COLOR][COLOR=#333333][FONT=Consolas]([/FONT][/COLOR][COLOR=#333333][FONT=Consolas]tmdsclk [/FONT][/COLOR][COLOR=#333333][FONT=Consolas][B]> [/B][/FONT][/COLOR][COLOR=#009999][FONT=Consolas]340000000[/FONT][/COLOR][COLOR=#333333][FONT=Consolas])
[/FONT][/COLOR]{
vpara[B]->[/B]color_output_depth [B]=[/B] [COLOR=#009999]8[/COLOR];
tmdsclk [B]=[/B] mode[B]->[/B]pixclock;
[COLOR=#333333][FONT=Consolas]}[/FONT][/COLOR]
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