Tutorial: Enable RK3368 True Octa-Core Processor - Part 1 of 2

[shomari_]

Proof of concept and idea explained here: http://freaktab.com/forum/tv-player-...tacore-release

1. Modify your device tree blob to alter the Rockchip big.LITTLE cluster and cpu topology

STOCK

[COLOR=#FF0000]-[/COLOR]    cluster0 {

                core0 {
                    cpu = <0x6a>;
                };

                core1 {
                    cpu = <0x6b>;
                };

                core2 {
                    cpu = <0x6c>;
                };

                core3 {
                    cpu = <0x6d>;
                };
            };

            cluster1 {

                core0 {
                    cpu = <0x6e>;
                };

                core1 {
                    cpu = <0x6f>;
                };

                core2 {
                    cpu = <0x70>;
                };

                core3 {
                    cpu = <0x71>;
                };

SHOMARI

[COLOR=#00FF00]+[/COLOR]    cluster0  [SIZE=12px]{[/SIZE]

                core0 {
                    cpu = <0x6e>;
                };

                core1 {
                    cpu = <0x6f>;
                };

                core2 {
                    cpu = <0x70>;
                };

                core3 {
                    cpu = <0x71>;
                };

                core4 {
                    cpu = <0x6a>;
                };

                core5 {
                    cpu = <0x6b>;
                };

                core6 {
                    cpu = <0x6c>;
                };

                core7 {
                    cpu = <0x6d>;
                };

2. Enable DVFS frequency shifting, set operating points, disable .LITTLE node

STOCK

[COLOR=#FF0000]-[/COLOR]    dvfs {

        vd_arm {
            regulator_name = "vdd_arm";
            suspend_volt = <0x3e8>;

            pd_core {

                clk_core_b {
                    operating-points = <0x4c2c0 0xf4240 0x639c0 0xf4240 0x927c0 0xf4240 0xa9ec0 0xf4240 0xc7380 0x10c8e0 0xf6180 0x10c8e0 0x124f80 0x11edd8 0x159b40 0x13d620 0x16b480 0x1437c8 0x171240 0x149970>;
                    status = "okay";
                    temp-limit-enable = <0x1>;
                    target-temp = <0x5a>;
                    min_temp_limit = <0x34bc0>;
                    normal-temp-limit = <0x3 0x17700 0x6 0x23280 0x9 0x2ee00 0xf 0x5dc00>;
                    performance-temp-limit = <0x64 0xc7380>;
                    lkg_adjust_volt_en = <0x1>;
                    channel = <0x0>;
                    tsadc-ch = <0x0>;
                    def_table_lkg = <0xa>;
                    min_adjust_freq = <0x34bc0>;
                    lkg_adjust_volt_table = <0x0 0x61a8 0x28 0x0 0x32 0x61a8 0x96 0xc350>;
                };

                clk_core_l {
                    operating-points = <0x4c2c0 0xf4240 0x639c0 0xf4240 0x927c0 0xf4240 0xa9ec0 0xf4240 0xc7380 0x10c8e0 0xf6180 0x124f80 0x124f80 0x1312d0>;
                    status = "okay";
                    temp-limit-enable = <0x1>;
                    target-temp = <0x5a>;
                    min_temp_limit = <0x34bc0>;
                    normal-temp-limit = <0x3 0x17700 0x6 0x23280 0x9 0x2ee00 0xf 0x5dc00>;
                    performance-temp-limit = <0x64 0xc7380>;
                    lkg_adjust_volt_en = <0x1>;
                    channel = <0x0>;
                    tsadc-ch = <0x0>;
                    def_table_lkg = <0xa>;
                    min_adjust_freq = <0x34bc0>;
                    lkg_adjust_volt_table = <0x0 0x61a8 0x28 0x0 0x32 0x61a8 0x96 0xc350>;
                };

SHOMARI

[COLOR=#00FF00]+[/COLOR]    dvfs {

        vd_arm {
            regulator_name = "vdd_arm";
            suspend_volt = <0x3e8>;

            pd_core {

                clk_core_b {
                    operating-points = <0xa9ec0 0xee098 0xc7380 0xf4240 0xf6180 0x10c8e0 0x124f80 0x11edd8 0x159b40 0x13d620 0x16b480 0x1437c8 0x171240 0x149970 0x188940 0x1535b0>;
                    status = "okay";
                    #cluster = <0x1>;
                    channel = <0x1>;
                    high_performance = <0x1>;
                    dev_mode = <0x0>;

                    clk_core_l {
                        operating-points = <0xa9ec0 0xee098 0xc7380 0x100590 0xf6180 0x112a88 0x124f80 0x1312d0 0x188940 0x162010>;
                        status = "disabled";
                        cluster = <0x1>;
                        temp-limit-enable = <0x1>;
                        target-temp = <0x50>;
                        min_temp_limit = <0x34bc0>;
                        normal-temp-limit = <0x3 0x17700 0x6 0x23280 0x9 0x2ee00 0xf 0x5dc00>;
                        performance-temp-limit = <0x64 0xc7380>;
                        lkg_adjust_volt_en = <0x1>;
                        channel = <0x1>;
                        tsadc-ch = <0x0>;
                        def_table_lkg = <0x19>;
                        min_adjust_freq = <0x34bc0>;
                        lkg_adjust_volt_table = <0x0 0x61a8 0x28 0x0 0x32 0x61a8 0x96 0xc350>;
                    };

http://freaktab.com/member/41233-shomari FOR RESEARCH PURPOSES ONLY

[l33tlinuxh4x0r]

What files are these exactly? How do I edit them (hexeditor, textediter)? And what is the build process(do I need to recompile the OS, the kernel, or everything)?

Thanks

[mo123]

What files are these exactly? How do I edit them (hexeditor, textediter)? And what is the build process(do I need to recompile the OS, the kernel, or everything)?

Thanks

You need to recompile the resource.img in Linux.

[l33tlinuxh4x0r]

You need to recompile the resource.img in Linux.

I thought that uboot needed to be updated too. Are all of the changes in resource.img?

ALSO where are the files located? I cant find any files that resemble what is shown in OP.

[mo123]

I thought that uboot needed to be updated too. Are all of the changes in resource.img?

ALSO where are the files located? I cant find any files that resemble what is shown in OP.

You need to modify the dts file in the resource.img and recompile it.

http://forum.geekbox.tv/viewtopic.php?f=2&t=27

[l33tlinuxh4x0r]

You need to modify the dts file in the resource.img and recompile it.
http://forum.geekbox.tv/viewtopic.php?f=2&t=27

Yeah, I followed those instructions before and was able to get a working android install with everything working however I still cannot find the above in any of the dts files. Could you please tell me exactly which dts file needs to be edited?

EDIT: I think that I just found the file. For future reference and for anyone else that needs to know. It is rk3368.dtsi and it is located in sourcedir/kernel/arch/arm64/boot/dts

Thanks for the help!

[mo123]

Yeah, I followed those instructions before and was able to get a working android install with everything working however I still cannot find the above in any of the dts files. Could you please tell me exactly which dts file needs to be edited?

rk3368-box.dts

[shomari_]

... sorry, just now seeing this. I'll send you a pm or we can discuss here. Either way, let me know.

I wrote this part assuming readers would have a certain knowledge of RK code. My apologies, but I can answer any questions if you need any help.

[l33tlinuxh4x0r]

... sorry, just now seeing this. I'll send you a pm or we can discuss here. Either way, let me know.

I wrote this part assuming readers would have a certain knowledge of RK code. My apologies, but I can answer any questions if you need any help.

I don't need a PM. I hadn't seen this thread and thought that you hadn't written a tutorial yet. Also what is going to be in part 2 of 2.

[shomari_]

I don't need a PM. I hadn't seen this thread and thought that you hadn't written a tutorial yet. Also what is going to be in part 2 of 2.

... observations, bugs, tools, etc.

EDIT: To explain, there's more to it than just the device tree source. HMP parameters have to be tuned at boot because we don't have a way to do it at kernel level thanks to RK being RK. Also, different devices have different implementations of the same functions, making universality not impossible, but varying degrees of difficult.

[CivicObligation]

How can these files be modified and recompiled in Windows 10 instead of Linux?

[l33tlinuxh4x0r]

How can these files be modified and recompiled in Windows 10 instead of Linux?

If you install Linux in windows. There is a subsystem for this in the latest builds of windows 10 that allows you to install ubuntu inside of windows. However it hasn't been tested with this and you might as well just dual boot.

[l33tlinuxh4x0r]

... observations, bugs, tools, etc.

EDIT: To explain, there's more to it than just the device tree source. HMP parameters have to be tuned at boot because we don't have a way to do it at kernel level thanks to RK being RK. Also, different devices have different implementations of the same functions, making universality not impossible, but varying degrees of difficult.

how do we edit the HMP parameters at boot? recompile uboot?

[l33tlinuxh4x0r]

I followed the instructions and all of the cores are running symmetrically now but they are stuck at 792Mhz. What is wrong?

I think that I found it! the following lines need to be changed too!


Original

    rockchip_clocks_init: clocks-init{
        compatible = "rockchip,clocks-init";
        rockchip,clocks-init-parent =
            <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
            <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
            <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
            <&clk_cs &clk_gpll>, <&clk_32k_mux &xin32k>;
        rockchip,clocks-init-rate =
            <&clk_gpll 576000000>,        <&clk_core_b 792000000>,
            <&clk_core_l 600000000>,    <&clk_cpll 400000000>,
            /*<&clk_npll 500000000>,*/    <&aclk_bus 300000000>,
            <&hclk_bus 150000000>,        <&pclk_bus 75000000>,
            <&clk_crypto 150000000>,    <&aclk_peri 300000000>,
            <&hclk_peri 150000000>,        <&pclk_peri 75000000>,
            <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
            <&clk_cs 300000000>,        <&clkin_trace 300000000>,
            <&aclk_cci 600000000>,        <&clk_mac 125000000>,
            <&aclk_vio0 400000000>,        <&hclk_vio 100000000>,
            <&aclk_rga_pre 400000000>,    <&clk_rga 400000000>,
            <&clk_isp 400000000>,        <&clk_edp 200000000>,
            <&clk_gpu_core 400000000>,    <&aclk_gpu_mem 400000000>,
            <&aclk_gpu_cfg 400000000>,    <&aclk_vepu 400000000>,
            <&aclk_vdpu 400000000>,        <&clk_hevc_core 300000000>,
            <&clk_hevc_cabac 300000000>;

Fixed

    rockchip_clocks_init: clocks-init{
        compatible = "rockchip,clocks-init";
        rockchip,clocks-init-parent =
            <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
            <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
            <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
            <&clk_cs &clk_gpll>, <&clk_32k_mux &xin32k>;
        rockchip,clocks-init-rate =
            <&clk_gpll 576000000>,        <&clk_core_b 1008000000>,
            <&clk_core_l 600000000>,    <&clk_cpll 400000000>,
            /*<&clk_npll 500000000>,*/    <&aclk_bus 300000000>,
            <&hclk_bus 150000000>,        <&pclk_bus 75000000>,
            <&clk_crypto 150000000>,    <&aclk_peri 300000000>,
            <&hclk_peri 150000000>,        <&pclk_peri 75000000>,
            <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
            <&clk_cs 300000000>,        <&clkin_trace 300000000>,
            <&aclk_cci 600000000>,        <&clk_mac 125000000>,
            <&aclk_vio0 400000000>,        <&hclk_vio 100000000>,
            <&aclk_rga_pre 400000000>,    <&clk_rga 400000000>,
            <&clk_isp 400000000>,        <&clk_edp 200000000>,
            <&clk_gpu_core 600000000>,    <&aclk_gpu_mem 600000000>,
            <&aclk_gpu_cfg 400000000>,    <&aclk_vepu 400000000>,
            <&aclk_vdpu 400000000>,        <&clk_hevc_core 300000000>,
            <&clk_hevc_cabac 300000000>;

The important variable is
<&clk_core_b 1008000000>, I'm slowly increasing it.


For some reason I cannot go past 1008000000, I want to go to 1512000000.
In android it shows as an available clock speed however it will now boot when i change it to 1512000000

I also changed <&clk_gpu_core 400000000>, to <&clk_gpu_core 600000000>, and that works. also did the same with gpu_mem

[Shomari]

I followed the instructions and all of the cores are running symmetrically now but they are stuck at 792Mhz. What is wrong?

I think that I found it! the following lines need to be changed too!


Original

rockchip_clocks_init: clocks-init{
compatible = "rockchip,clocks-init";
rockchip,clocks-init-parent =
<&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
<&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
<&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
<&clk_cs &clk_gpll>, <&clk_32k_mux &xin32k>;
rockchip,clocks-init-rate =
<&clk_gpll 576000000>, <&clk_core_b 792000000>,
<&clk_core_l 600000000>, <&clk_cpll 400000000>,
/*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
<&hclk_bus 150000000>, <&pclk_bus 75000000>,
<&clk_crypto 150000000>, <&aclk_peri 300000000>,
<&hclk_peri 150000000>, <&pclk_peri 75000000>,
<&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
<&clk_cs 300000000>, <&clkin_trace 300000000>,
<&aclk_cci 600000000>, <&clk_mac 125000000>,
<&aclk_vio0 400000000>, <&hclk_vio 100000000>,
<&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
<&clk_isp 400000000>, <&clk_edp 200000000>,
<&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
<&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
<&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
<&clk_hevc_cabac 300000000>;

Fixed

rockchip_clocks_init: clocks-init{
compatible = "rockchip,clocks-init";
rockchip,clocks-init-parent =
<&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
<&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
<&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
<&clk_cs &clk_gpll>, <&clk_32k_mux &xin32k>;
rockchip,clocks-init-rate =
<&clk_gpll 576000000>, <&clk_core_b 1008000000>,
<&clk_core_l 600000000>, <&clk_cpll 400000000>,
/*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
<&hclk_bus 150000000>, <&pclk_bus 75000000>,
<&clk_crypto 150000000>, <&aclk_peri 300000000>,
<&hclk_peri 150000000>, <&pclk_peri 75000000>,
<&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
<&clk_cs 300000000>, <&clkin_trace 300000000>,
<&aclk_cci 600000000>, <&clk_mac 125000000>,
<&aclk_vio0 400000000>, <&hclk_vio 100000000>,
<&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
<&clk_isp 400000000>, <&clk_edp 200000000>,
<&clk_gpu_core 600000000>, <&aclk_gpu_mem 600000000>,
<&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
<&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
<&clk_hevc_cabac 300000000>;

The important variable is
<&clk_core_b 1008000000>, I'm slowly increasing it.


For some reason I cannot go past 1008000000, I want to go to 1512000000.
In android it shows as an available clock speed however it will now boot when i change it to 1512000000

I also changed <&clk_gpu_core 400000000>, to <&clk_gpu_core 600000000>, and that works. also did the same with gpu_mem

... yes, indeed. Keep at it, the performance gains are very much worth it. One word of note, be mindful of the voltage levels as anything above a certain point will require a more powerful power adapter. I run my boxes at 1608 and GPU at 624 and I use a 4a power supply to do so. You also have to be sure to alter (or eliminate altogether, like I do) the thermal arrests and deactivate/activate the appropriate clusters at the node level.

I'll be around tomorrow with some more info and posts. Good luck!