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Tutorial: Enable RK3368 True Octa-Core Processor - Part 1 of 2

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    #31
    Shomari I just flashed the stock geekbox kernel (built without any modifications) and I get the same errors about dvfs not being enabled. I get it for core b and core l which is to be expected. Something in their sources (the same source that I'm using) is disabling dvfs. I am looking for new kernel sources now.

    Comment

      #32
      I found why this was spamming the log.
      Code:
      [   37.649728]  [1:  cfinteractive:   79] DVFS ERR:    dvfs_target: clk_core_b is disable, set rate error
      It was the interactive governor trying to change things all of the time. I changed it to performance and the spam stopped.
      Code:
      [   30.818006]  [2:             sh:  615] -------------DVFS TREE-----------
[   30.818006]  [2:             sh:  615]
[   30.818006]  [2:             sh:  615]
[   30.818089]  [2:             sh:  615] DVFS TREE:
[   30.818115]  [2:             sh:  615] |
[   30.818115]  [2:             sh:  615] |- voltage domain:vd_logic
[   30.818159]  [2:             sh:  615] |- current voltage:0
[   30.818184]  [2:             sh:  615] |- current regu_mode:UNKNOWN
[   30.818213]  [2:             sh:  615] |  |
[   30.818213]  [2:             sh:  615] |  |- power domain:pd_gpu, status = OFF, current volt = 0, current regu_mode = UNKNOWN
[   30.818263]  [2:             sh:  615] |  |  |
[   30.818263]  [2:             sh:  615] |  |  |- clock: clk_gpu current: rate 0, volt = 0, enable_dvfs = DISABLE
[   30.818313]  [2:             sh:  615] |  |  |- clk limit(disable):[0, 0]; last set rate = 200000
[   30.818341]  [2:             sh:  615] |  |  |  |- freq = 200000, volt = 1200000
[   30.818368]  [2:             sh:  615] |  |  |  |- freq = 300000, volt = 1200000
[   30.818395]  [2:             sh:  615] |  |  |  |- freq = 400000, volt = 1200000
[   30.818421]  [2:             sh:  615] |  |  |  |- freq = 600000, volt = 1200000
[   30.818450]  [2:             sh:  615] |  |  |- clock: clk_gpu current: rate 0, regu_mode = UNKNOWN, regu_mode_en = 0
[   30.818481]  [2:             sh:  615] |  |
[   30.818481]  [2:             sh:  615] |  |- power domain:pd_ddr, status = OFF, current volt = 0, current regu_mode = UNKNOWN
[   30.818531]  [2:             sh:  615] |  |  |
[   30.818531]  [2:             sh:  615] |  |  |- clock: clk_ddr current: rate 0, volt = 0, enable_dvfs = DISABLE
[   30.818582]  [2:             sh:  615] |  |  |- clk limit(disable):[0, 0]; last set rate = 600000
[   30.818877]  [2:             sh:  615] |  |  |  |- freq = 200000, volt = 1200000
[   30.818917]  [2:             sh:  615] |  |  |  |- freq = 300000, volt = 1200000
[   30.818944]  [2:             sh:  615] |  |  |  |- freq = 400000, volt = 1200000
[   30.818972]  [2:             sh:  615] |  |  |  |- freq = 533000, volt = 1150000
[   30.818999]  [2:             sh:  615] |  |  |  |- freq = 800000, volt = 1200000
[   30.819027]  [2:             sh:  615] |  |  |- clock: clk_ddr current: rate 0, regu_mode = UNKNOWN, regu_mode_en = 0
[   30.819057]  [2:             sh:  615] |
[   30.819057]  [2:             sh:  615] |- voltage domain:vd_arm
[   30.819103]  [2:             sh:  615] |- current voltage:0
[   30.819128]  [2:             sh:  615] |- current regu_mode:UNKNOWN
[   30.819158]  [2:             sh:  615] |  |
[   30.819158]  [2:             sh:  615] |  |- power domain:pd_core, status = OFF, current volt = 0, current regu_mode = UNKNOWN
[   30.819208]  [2:             sh:  615] |  |  |
[   30.819208]  [2:             sh:  615] |  |  |- clock: clk_core_b current: rate 0, volt = 0, enable_dvfs = DISABLE
[   30.819259]  [2:             sh:  615] |  |  |- clk limit(enable):[216000000, 1608000000]; last set rate = 1512000
[   30.819288]  [2:             sh:  615] |  |  |  |- freq = 216000, volt = 950000
[   30.819317]  [2:             sh:  615] |  |  |  |- freq = 312000, volt = 950000
[   30.819344]  [2:             sh:  615] |  |  |  |- freq = 408000, volt = 950000
[   30.819370]  [2:             sh:  615] |  |  |  |- freq = 600000, volt = 975000
[   30.819396]  [2:             sh:  615] |  |  |  |- freq = 696000, volt = 975000
[   30.819423]  [2:             sh:  615] |  |  |  |- freq = 816000, volt = 1000000
[   30.819450]  [2:             sh:  615] |  |  |  |- freq = 1008000, volt = 1100000
[   30.819477]  [2:             sh:  615] |  |  |  |- freq = 1200000, volt = 1175000
[   30.819504]  [2:             sh:  615] |  |  |  |- freq = 1416000, volt = 1300000
[   30.819531]  [2:             sh:  615] |  |  |  |- freq = 1488000, volt = 1325000
[   30.819558]  [2:             sh:  615] |  |  |  |- freq = 1512000, volt = 1350000
[   30.819585]  [2:             sh:  615] |  |  |  |- freq = 1608000, volt = 1390000
[   30.819613]  [2:             sh:  615] |  |  |- clock: clk_core_b current: rate 0, regu_mode = UNKNOWN, regu_mode_en = 0
[   30.819641]  [2:             sh:  615] -------------DVFS TREE END------------
      Current dvfs issues. I don't think that it is dvfs that is the issue. I think that it has something to do with cpufreq. If I disable cpufreq in the kernel the error messages go away but I cannot set or view the clock of the cpu anymore.




      EDIT:
      Current errors:
      Code:
      [    2.799884]  [0:      swapper/0:    1] DVFS ERR:    clk_enable_dvfs: vd(vd_logic) can't get regulator(vdd_logic)!
[    2.799917]  [0:      swapper/0:    1] DVFS ERR:    clk_enable_dvfs: vd(vd_logic) can't get regulator(vdd_logic)!
[    2.799950]  [0:      swapper/0:    1] DVFS ERR:    clk_enable_dvfs: vd(vd_arm) can't get regulator(vdd_arm)!
[    2.799979]  [0:      swapper/0:    1] rockchip_big_little: cluster_cpus_freq_dvfs_init:cluster_id=1,get dvfs err
[    2.800987]  [0:      swapper/0:    1] DVFS ERR:    dvfs_target: clk_core_b is disable, set rate error
[    2.801019]  [0:      swapper/0:    1] DVFS ERR:    dvfs_target: clk_core_b is disable, set rate error
[    2.968106]  [1:      swapper/0:    1] DVFS ERR:    clk_enable_dvfs: vd(vd_logic) can't get regulator(vdd_logic)!
[    2.968810]  [0:       ddrfreqd:  137] DVFS ERR:    dvfs_target: clk_ddr is disable, set rate error
[    3.337357]  [7:           init:    1] DVFS ERR:    dvfs_target: clk_core_b is disable, set rate error
[    3.337600]  [7:           init:    1] DVFS ERR:    dvfs_target: clk_core_b is disable, set rate error
[    5.163547]  [1:      pvrsrvctl:  183] rgx_dvfs_infotbl[0].clock=200,min_threshold=0,max_threshold=40,coef=100
[    5.163584]  [1:      pvrsrvctl:  183] rgx_dvfs_infotbl[1].clock=300,min_threshold=50,max_threshold=60,coef=95
[    5.163617]  [1:      pvrsrvctl:  183] rgx_dvfs_infotbl[2].clock=400,min_threshold=70,max_threshold=80,coef=90
[    5.163651]  [1:      pvrsrvctl:  183] rgx_dvfs_infotbl[3].clock=600,min_threshold=86,max_threshold=100,coef=85
[    5.163854]  [1:      pvrsrvctl:  183] DVFS ERR:    dvfs_target: clk_gpu is disable, set rate error
[    5.189547]  [4:      pvrsrvctl:  183] DVFS ERR:    dvfs_target: clk_gpu is disable, set rate error
[   16.597631]  [3:  system_server:  605] DVFS ERR:    dvfs_target: clk_core_b is disable, set rate error
[   36.782223]  [3:           init:    1] DVFS ERR:    dvfs_target: clk_core_b is disable, set rate error
[   36.783799]  [3:           init:    1] DVFS ERR:    dvfs_target: clk_core_b is disable, set rate error
      the first three lines are the important ones! Apparently the voltage regulator isn't enabled or configured correctly.
      Last edited by l33tlinuxh4x0r; 09 December 2016, 03:59.

      Comment

        #33
        Originally posted by l33tlinuxh4x0r View Post
        I found why this was spamming the log.
        Code:
        [ 37.649728] [1: cfinteractive: 79] DVFS ERR: dvfs_target: clk_core_b is disable, set rate error
        It was the interactive governor trying to change things all of the time. I changed it to performance and the spam stopped.
        Code:
        [ 30.818006] [2: sh: 615] -------------DVFS TREE-----------
[ 30.818006] [2: sh: 615]
[ 30.818006] [2: sh: 615]
[ 30.818089] [2: sh: 615] DVFS TREE:
[ 30.818115] [2: sh: 615] |
[ 30.818115] [2: sh: 615] |- voltage domain:vd_logic
[ 30.818159] [2: sh: 615] |- current voltage:0
[ 30.818184] [2: sh: 615] |- current regu_mode:UNKNOWN
[ 30.818213] [2: sh: 615] | |
[ 30.818213] [2: sh: 615] | |- power domain:pd_gpu, status = OFF, current volt = 0, current regu_mode = UNKNOWN
[ 30.818263] [2: sh: 615] | | |
[ 30.818263] [2: sh: 615] | | |- clock: clk_gpu current: rate 0, volt = 0, enable_dvfs = DISABLE
[ 30.818313] [2: sh: 615] | | |- clk limit(disable):[0, 0]; last set rate = 200000
[ 30.818341] [2: sh: 615] | | | |- freq = 200000, volt = 1200000
[ 30.818368] [2: sh: 615] | | | |- freq = 300000, volt = 1200000
[ 30.818395] [2: sh: 615] | | | |- freq = 400000, volt = 1200000
[ 30.818421] [2: sh: 615] | | | |- freq = 600000, volt = 1200000
[ 30.818450] [2: sh: 615] | | |- clock: clk_gpu current: rate 0, regu_mode = UNKNOWN, regu_mode_en = 0
[ 30.818481] [2: sh: 615] | |
[ 30.818481] [2: sh: 615] | |- power domain:pd_ddr, status = OFF, current volt = 0, current regu_mode = UNKNOWN
[ 30.818531] [2: sh: 615] | | |
[ 30.818531] [2: sh: 615] | | |- clock: clk_ddr current: rate 0, volt = 0, enable_dvfs = DISABLE
[ 30.818582] [2: sh: 615] | | |- clk limit(disable):[0, 0]; last set rate = 600000
[ 30.818877] [2: sh: 615] | | | |- freq = 200000, volt = 1200000
[ 30.818917] [2: sh: 615] | | | |- freq = 300000, volt = 1200000
[ 30.818944] [2: sh: 615] | | | |- freq = 400000, volt = 1200000
[ 30.818972] [2: sh: 615] | | | |- freq = 533000, volt = 1150000
[ 30.818999] [2: sh: 615] | | | |- freq = 800000, volt = 1200000
[ 30.819027] [2: sh: 615] | | |- clock: clk_ddr current: rate 0, regu_mode = UNKNOWN, regu_mode_en = 0
[ 30.819057] [2: sh: 615] |
[ 30.819057] [2: sh: 615] |- voltage domain:vd_arm
[ 30.819103] [2: sh: 615] |- current voltage:0
[ 30.819128] [2: sh: 615] |- current regu_mode:UNKNOWN
[ 30.819158] [2: sh: 615] | |
[ 30.819158] [2: sh: 615] | |- power domain:pd_core, status = OFF, current volt = 0, current regu_mode = UNKNOWN
[ 30.819208] [2: sh: 615] | | |
[ 30.819208] [2: sh: 615] | | |- clock: clk_core_b current: rate 0, volt = 0, enable_dvfs = DISABLE
[ 30.819259] [2: sh: 615] | | |- clk limit(enable):[216000000, 1608000000]; last set rate = 1512000
[ 30.819288] [2: sh: 615] | | | |- freq = 216000, volt = 950000
[ 30.819317] [2: sh: 615] | | | |- freq = 312000, volt = 950000
[ 30.819344] [2: sh: 615] | | | |- freq = 408000, volt = 950000
[ 30.819370] [2: sh: 615] | | | |- freq = 600000, volt = 975000
[ 30.819396] [2: sh: 615] | | | |- freq = 696000, volt = 975000
[ 30.819423] [2: sh: 615] | | | |- freq = 816000, volt = 1000000
[ 30.819450] [2: sh: 615] | | | |- freq = 1008000, volt = 1100000
[ 30.819477] [2: sh: 615] | | | |- freq = 1200000, volt = 1175000
[ 30.819504] [2: sh: 615] | | | |- freq = 1416000, volt = 1300000
[ 30.819531] [2: sh: 615] | | | |- freq = 1488000, volt = 1325000
[ 30.819558] [2: sh: 615] | | | |- freq = 1512000, volt = 1350000
[ 30.819585] [2: sh: 615] | | | |- freq = 1608000, volt = 1390000
[ 30.819613] [2: sh: 615] | | |- clock: clk_core_b current: rate 0, regu_mode = UNKNOWN, regu_mode_en = 0
[ 30.819641] [2: sh: 615] -------------DVFS TREE END------------
        Current dvfs issues. I don't think that it is dvfs that is the issue. I think that it has something to do with cpufreq. If I disable cpufreq in the kernel the error messages go away but I cannot set or view the clock of the cpu anymore.




        EDIT:
        Current errors:
        Code:
        [ 2.799884] [0: swapper/0: 1] DVFS ERR: clk_enable_dvfs: vd(vd_logic) can't get regulator(vdd_logic)!
[ 2.799917] [0: swapper/0: 1] DVFS ERR: clk_enable_dvfs: vd(vd_logic) can't get regulator(vdd_logic)!
[ 2.799950] [0: swapper/0: 1] DVFS ERR: clk_enable_dvfs: vd(vd_arm) can't get regulator(vdd_arm)!
[ 2.799979] [0: swapper/0: 1] rockchip_big_little: cluster_cpus_freq_dvfs_init:cluster_id=1,get dvfs err
[ 2.800987] [0: swapper/0: 1] DVFS ERR: dvfs_target: clk_core_b is disable, set rate error
[ 2.801019] [0: swapper/0: 1] DVFS ERR: dvfs_target: clk_core_b is disable, set rate error
[ 2.968106] [1: swapper/0: 1] DVFS ERR: clk_enable_dvfs: vd(vd_logic) can't get regulator(vdd_logic)!
[ 2.968810] [0: ddrfreqd: 137] DVFS ERR: dvfs_target: clk_ddr is disable, set rate error
[ 3.337357] [7: init: 1] DVFS ERR: dvfs_target: clk_core_b is disable, set rate error
[ 3.337600] [7: init: 1] DVFS ERR: dvfs_target: clk_core_b is disable, set rate error
[ 5.163547] [1: pvrsrvctl: 183] rgx_dvfs_infotbl[0].clock=200,min_threshold=0,max_threshold=40,coef=100
[ 5.163584] [1: pvrsrvctl: 183] rgx_dvfs_infotbl[1].clock=300,min_threshold=50,max_threshold=60,coef=95
[ 5.163617] [1: pvrsrvctl: 183] rgx_dvfs_infotbl[2].clock=400,min_threshold=70,max_threshold=80,coef=90
[ 5.163651] [1: pvrsrvctl: 183] rgx_dvfs_infotbl[3].clock=600,min_threshold=86,max_threshold=100,coef=85
[ 5.163854] [1: pvrsrvctl: 183] DVFS ERR: dvfs_target: clk_gpu is disable, set rate error
[ 5.189547] [4: pvrsrvctl: 183] DVFS ERR: dvfs_target: clk_gpu is disable, set rate error
[ 16.597631] [3: system_server: 605] DVFS ERR: dvfs_target: clk_core_b is disable, set rate error
[ 36.782223] [3: init: 1] DVFS ERR: dvfs_target: clk_core_b is disable, set rate error
[ 36.783799] [3: init: 1] DVFS ERR: dvfs_target: clk_core_b is disable, set rate error
        the first three lines are the important ones! Apparently the voltage regulator isn't enabled or configured correctly.
        Can you upload your compiled resource image please? I want to take a look, I'll be able to tell what's not right and perhaps you can recompile and correct your values to get it working properly. I don't have my workstation set up to work from source at the moment so it's the best I can do given my unfamiliarity with that source code.

        Comment

          #34
          Originally posted by l33tlinuxh4x0r View Post
          Shomari I just flashed the stock geekbox kernel (built without any modifications) and I get the same errors about dvfs not being enabled. I get it for core b and core l which is to be expected. Something in their sources (the same source that I'm using) is disabling dvfs. I am looking for new kernel sources now.
          because your issue is in the parameters being improperly set in resource. img

          Comment

            #35
            Eventually, once you get it right, the fun part begins when you get to play with the hmp tunables. There's probably even more performance to squeeze from the cpu itself if hmp is carefully tuned. I've stopped experimenting with that part until I eliminate the bug that causes the system to be unable to reboot/power down properly

            Comment

              #36
              I am wondering... You got the linux source code from kernel.org and you built it? What version of the kernel did you use (4.9-r8)? If so what did you so to do so. Obviously you cross compiled it but other than that what commands did you use?

              I have been using
              Code:
              make geekbox_defconfig
make geekbox.img -j8
./upgrade_tool DI kernel kernel.img
./upgrade_tool DI resource resource.img
./upgrade_tool RD
              Can I also get your kernel config or def_config? thanks.
              Last edited by l33tlinuxh4x0r; 09 December 2016, 05:53.

              Comment

                #37
                Ok, I got it working! Here is how I did it...
                I unpacked the stock update.img and then unpacked the stock resource.img from that. That gave me a dtb file and the logo.bmp for the kernel. I then de-compiled the dtb to a dts file. I made the modifications in the OP and compiled it. I will post my modified files for the geekbox sources in a couple of hours.

                Code:
                make geekbox_defconfig
make rk-kernel-oc.img -j8
./upgrade_tool DI kernel kernel.img
./upgrade_tool DI resource resource.img
./upgrade_tool RD
                ~30 seconds later it booted! now to test on the TV instead of with adb.

                EDIT: Very unstable have to iron out the kinks. I'll report back when I get it working stable.
                Last edited by l33tlinuxh4x0r; 09 December 2016, 20:00.

                Comment

                  #38
                  OK how I did it. Stable at 1416Mhz all 8 cores!
                  First I had to download the source code. It contains all of the source for android 6.0 as well if you are interested.
                  Code:
                  cd ~/project/
wget https://raw.githubusercontent.com/geekboxzone/mmallow/geekbox/repoinit.sh
chmod +x repoinit.sh
./repoinit.sh
                  More info on that can be found here http://forum.geekbox.tv/viewtopic.php?f=12&t=14 Also there is a bug in the source code as of this being written. You need to fix it. More on that later. API version and webrtc fails to build so you need to replace it if you are building android. IF you are just building the kernel then ignore this comment.
                  Back to the kernel you can either extract your resource.img and your *.dtb to make a *.dts or you can just use mine and edit it as needed for your device. You also need a kernel config. I have included both. Just drop them in ~/project/geekbox/mmallow/kernel/arch/arm64/
                  Then you can build the kernel with the following commands...
                  Code:
                  make overclock_defconfig
make rk-kernel-oc.img -j8
                  All should be good just flash your kernel.img and resource.img with whatever tool you usually use. I put upgrade_tool in my ~/project/geekbox/mmallow/kernel folder and do the following to flash after the kernel is built.
                  Code:
                  ./upgrade_tool DI kernel kernel.img && ./upgrade_tool DI resource resource.img && ./upgrade_tool RD
                  Hope that this helps.

                  Just extract my kernel.zip into your source folder and it should put the files in the correct places.


                  Here is a dmesg from what I'm currently running.
                  Code:
                  [  114.734217]  [7:             sh: 1434] -------------DVFS TREE-----------
[  114.734217]  [7:             sh: 1434]
[  114.734217]  [7:             sh: 1434]
[  114.734261]  [7:             sh: 1434] DVFS TREE:
[  114.734272]  [7:             sh: 1434] |
[  114.734272]  [7:             sh: 1434] |- voltage domain:vd_logic
[  114.734290]  [7:             sh: 1434] |- current voltage:1000000
[  114.734300]  [7:             sh: 1434] |- current regu_mode:UNKNOWN
[  114.734312]  [7:             sh: 1434] |  |
[  114.734312]  [7:             sh: 1434] |  |- power domain:pd_gpu, status = OFF, current volt = 950000, current regu_mode = UNKNOWN
[  114.734333]  [7:             sh: 1434] |  |  |
[  114.734333]  [7:             sh: 1434] |  |  |- clock: clk_gpu current: rate 288000, volt = 950000, enable_dvfs = ENABLE
[  114.734353]  [7:             sh: 1434] |  |  |- clk limit(enable):[288000000, 576000000]; last set rate = 288000
[  114.734365]  [7:             sh: 1434] |  |  |  |- freq = 288000, volt = 950000
[  114.734376]  [7:             sh: 1434] |  |  |  |- freq = 400000, volt = 950000
[  114.734387]  [7:             sh: 1434] |  |  |  |- freq = 576000, volt = 975000
[  114.734398]  [7:             sh: 1434] |  |  |- clock: clk_gpu current: rate 288000, regu_mode = UNKNOWN, regu_mode_en = 0
[  114.734412]  [7:             sh: 1434] |  |
[  114.734412]  [7:             sh: 1434] |  |- power domain:pd_ddr, status = OFF, current volt = 1000000, current regu_mode = UNKNOWN
[  114.734433]  [7:             sh: 1434] |  |  |
[  114.734433]  [7:             sh: 1434] |  |  |- clock: clk_ddr current: rate 792000, volt = 1000000, enable_dvfs = ENABLE
[  114.734453]  [7:             sh: 1434] |  |  |- clk limit(enable):[200000000, 800000000]; last set rate = 792000
[  114.734465]  [7:             sh: 1434] |  |  |  |- freq = 200000, volt = 950000
[  114.734475]  [7:             sh: 1434] |  |  |  |- freq = 300000, volt = 950000
[  114.734486]  [7:             sh: 1434] |  |  |  |- freq = 400000, volt = 950000
[  114.734497]  [7:             sh: 1434] |  |  |  |- freq = 600000, volt = 975000
[  114.734533]  [7:             sh: 1434] |  |  |  |- freq = 800000, volt = 1000000
[  114.734546]  [7:             sh: 1434] |  |  |- clock: clk_ddr current: rate 792000, regu_mode = UNKNOWN, regu_mode_en = 0
[  114.734558]  [7:             sh: 1434] |
[  114.734558]  [7:             sh: 1434] |- voltage domain:vd_arm
[  114.734577]  [7:             sh: 1434] |- current voltage:1300000
[  114.734654]  [7:             sh: 1434] |- current regu_mode:UNKNOWN
[  114.734707]  [7:             sh: 1434] |  |
[  114.734707]  [7:             sh: 1434] |  |- power domain:pd_core, status = OFF, current volt = 1300000, current regu_mode = UNKNOWN
[  114.734768]  [7:             sh: 1434] |  |  |
[  114.734768]  [7:             sh: 1434] |  |  |- clock: clk_core_b current: rate 1512000, volt = 1300000, enable_dvfs = ENABLE
[  114.734818]  [7:             sh: 1434] |  |  |- clk limit(enable):[216000000, 1512000000]; last set rate = 1512000
[  114.734881]  [7:             sh: 1434] |  |  |  |- freq = 216000, volt = 950000
[  114.734922]  [7:             sh: 1434] |  |  |  |- freq = 312000, volt = 950000
[  114.734964]  [7:             sh: 1434] |  |  |  |- freq = 408000, volt = 950000
[  114.735015]  [7:             sh: 1434] |  |  |  |- freq = 600000, volt = 975000
[  114.735077]  [7:             sh: 1434] |  |  |  |- freq = 696000, volt = 975000
[  114.735118]  [7:             sh: 1434] |  |  |  |- freq = 816000, volt = 1000000
[  114.735159]  [7:             sh: 1434] |  |  |  |- freq = 1008000, volt = 1125000
[  114.735182]  [7:             sh: 1434] |  |  |  |- freq = 1200000, volt = 1200000
[  114.735192]  [7:             sh: 1434] |  |  |  |- freq = 1416000, volt = 1225000
[  114.735204]  [7:             sh: 1434] |  |  |  |- freq = 1488000, volt = 1250000
[  114.735215]  [7:             sh: 1434] |  |  |  |- freq = 1512000, volt = 1300000
[  114.735227]  [7:             sh: 1434] |  |  |- clock: clk_core_b current: rate 1512000, regu_mode = UNKNOWN, regu_mode_en = 0
[  114.735238]  [7:             sh: 1434] -------------DVFS TREE END------------
                  That shows the clocks and volts being used. As you can see I have 1.5Ghz working stable!

                  Still working on increasing the clock speed. So far I have reached 1560Mhz or 1.56Ghz
                  Attached Files
                  Last edited by l33tlinuxh4x0r; 10 December 2016, 16:16.

                  Comment

                    #39
                    I am currently trying to disable big LITTLE cpufreq in favor of the stock rockchip cpufreq to see if that helps with scaling.
                    If I knew how to adjust the dvfs tables to work with the other cpufreq it might help. For now I'm going back to what works
                    Last edited by l33tlinuxh4x0r; 10 December 2016, 22:13.

                    Comment

                      #40
                      I have achieved 43726 in antutu and I have everything else working too! 1.56Ghz with the stock power supply! Big thanks to Shomari for this tutorial and to followmsi1 over at the geekbox forums for TWRP!

                      EDIT: I'm uploading my current configs if you want to build the kernel too!
                      Attached Files
                      Last edited by l33tlinuxh4x0r; 12 December 2016, 02:47.

                      Comment

                        #41
                        Originally posted by l33tlinuxh4x0r View Post
                        I have achieved 43726 in antutu and I have everything else working too! 1.56Ghz with the stock power supply! Big thanks to Shomari for this tutorial and to followmsi1 over at the geekbox forums for TWRP!

                        EDIT: I'm uploading my current configs if you want to build the kernel too!
                        ... nice!

                        Disable throttling in boot.img, init.rc

                        set the following parameter to '0' (off) from the default '1' (on):

                        write /sys/module/rockchip_pm/parameters/policy 0

                        Comment

                          #42
                          If you get any reboots or freezing, check your logs. It's either segfaults or power supply issues. Power supply issues can be suspected if the screen goes black and the box goes straight to off during intense multithreading tests.

                          Comment

                            #43
                            $64K question: do you have the reboot bug that crept back into my code, or is yours clean?

                            Comment

                              #44
                              ... also - change your cpu mem alignment in init.rc from the default '4' to 1 or 0. That'll help with the segfaults causing reboots during some benchmarks.

                              Comment

                                #45
                                Originally posted by Shomari View Post
                                ... nice!

                                Disable throttling in boot.img, init.rc

                                set the following parameter to '0' (off) from the default '1' (on):

                                write /sys/module/rockchip_pm/parameters/policy 0
                                That line doesn't even exist in my init.rc! I guess that means it is already off

                                EDIT: found it in another init file.

                                Also I am changing cpu mem alignment to 0.
                                Last edited by l33tlinuxh4x0r; 13 December 2016, 19:33.

                                Comment

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